This invention relates to a correlator and method for correlating, and more particularly, to a correlator and method of correlating in phase (I) and quadrature (Q) signal data.
Correlators are often used in many different types of processing systems, such as a tracking and location system, where time and angle of arrival have to be determined. Other information can be correlated, such as video and radar signals, as well as tracking and location information. In one proposed tracking and location system, a chirp waveform can be processed with an oscillator and associated circuits to increase the bandwidth. A correlator can be used as a matched filter for processing the chirp waveform, including the step of demodulating the chirp waveform.
One type of complex correlator has a basic function. It compares a reference to an incoming signal and gives a complex correlation. In emerging technologies, it is desirable to handle high data rates, such as four megabits a second. Correlators, however, become much more complicated when a quadrature input is required, e.g., an I and Q input, not just a real input. For example, a video correlator may have a channel data in and quantisizes a number of bits and correlates 1,000 samples of single points. It is necessary, however, when quadrature inputs are used to perform a cross correlation, which increases complexity. It is necessary to compare complex reference points to incoming data and determine a value, and then correlate more data again, such as 250 nanoseconds later.
Typically, larger correlators run slower. When correlators at a very low data rate, it is possible to take the data in and calculate thousands of point correlations. The time involved is extensive. These prior art types of correlators had difficulty reaching high rates, such as 4 Mbs. There was no optimal solution found between parallel and serial data flow, nor the loading of references.
Additionally, prior art correlators typically cannot be cascaded. Cascading correlator chips is relevant for complex correlators that have I and Q quadrature channels. Having these two channels will usually double the size of the gates and increase the complexity of multiplexers. As to the cascading of multiple correlator chips in the past, if a correlator had 1,000 samples and it was necessary to have 2,000 samples, a designer would take two 1,000 sample correlators, input the data, and then run through a delay with a shift register or RAM based delay and feed it to two chips. Additionally, reference data were not efficiently loaded, and storage of data and references using traditional shift register flip flops was not efficient.
It is therefore an object of the present invention to provide a correlator with an enhanced serial-parallel partition where different sets of correlation operations are performed in parallel and serially to reduce correlation length and increase speed in an optimum partition.
The correlator of the present invention includes a circuit for serially receiving in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels at one input bit time periods and converting the data into blocks of n bit parallel I and n bit parallel Q signal data. A data bus receives blocks of n bit parallel I and n bit parallel Q signal data and n bit parallel I and n bit parallel Q reference data from respective I and Q signal channels and I and Q reference channels. The data bus has n parallel paths extending therefrom.
A multiplexer is connected within each of the n parallel paths. Each multiplexer receives the n bit parallel I and Q reference data and a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path. Each multiplexer includes I and Q summed outputs based on the value of I and Q reference data on a bit-by-bit basis.
An n bit Wallace Tree Adder is connected to each of the I and Q summed outputs for each multiplexer within each of the n parallel paths that computes a count based on the number of bits that are set out of n bits to form partial correlation products. An adder and an accumulator register are in feedback with the adder adds the partial correlation products into a single sum. An output bus receives pairs of I and Q component signal outputs from the parallel paths one at a time at one input bit time period such that there is one correlation product output for every I and Q pair of input bits.
In still another aspect of the present invention, the adder and register comprise an m bit adder and register. The number m is a number less than n. In one aspect of the present invention, the m bits are about six bits, such as a six-bit Wallace Tree Adder, while the number n corresponds to 32 bits.
In still another aspect of the present invention, a counter can be operatively connected to the adder that is incremented by the counter whenever the addition of two m bit numbers results in an overflow. A register can be operatively connected to the accumulator register in the counter and is latched by the output of the accumulator register and counter.
In still another aspect of the present invention, a memory circuit receives and stores within each I and Q signal channel a current block of n bit parallel I and n bit parallel Q signal data and an immediately previously received block of n bit parallel I and n bit parallel Q signal data. This memory circuit comprises a circular buffer circuit, which can include a random access memory that receives the respective current block of n bit parallel I and Q signal data and overwrites the respective previous block of n bit parallel I and Q signal data. A multiplexer is operative with the random access memory and first and second registers store the respective current and previous blocks of n bit parallel I and Q signal data.
In still another aspect of the present invention, at least one programmable read only memory (PROM) stores I and Q reference data and means is connected to the at least one programmable read only memory along I and Q reference channels for converting the I and Q reference data to n bit parallel I and n bit parallel Q reference data upon power up of the correlator. At least one serial-to-parallel conversion register is also positioned within each I and Q reference channel and serially receives the respective I and Q reference data and converts the reference data to respective n bit parallel I and n bit parallel Q reference data within respective I and Q reference channels.
At least one serial-to-parallel conversion register is positioned within each I and Q signal channel and serially receives the respective I and Q signal data and converts the respective I and Q signal data to respective n bit parallel I and n bit parallel Q signal data within respective I and Q signal channels. At least one random access memory is positioned within each of the I and Q signal channels and receives sequences of n bit parallel I and n bit parallel Q reference data within I and Q signal channels based on predetermined clock cycles.
A method of the present invention correlates a signal having an in phase (I) and quadrature (Q) signal components and comprises the step of receiving on a data bus blocks of n bit parallel I and n bit parallel Q signal data and n bit parallel I and n bit parallel Q reference data from respective I and Q signal channels and I and Q reference channels. The data bus has n parallel paths extending therefrom. The method also comprises the step of multiplexing the I and Q reference data within each of the n parallel paths with a one bit shifted version of the respective n bit parallel I and n bit parallel Q signal data from an adjacent previous path to produce I and Q summed outputs based on the value of I and Q reference data on a bit-by-bit basis.
The method also comprises the step of inputting the I and Q summed outputs into respective Wallace Tree Adders that are connected to each of the I and Q summed outputs within each of the parallel paths and computing a count based on the number of bits that are set out of n bits. The partial correlation products are added into a single sum. Pairs of I and Q component signal outputs are received from the parallel paths one at a time at one input bit time periods such that there is one correlation product output for every I and Q pair of input bits.